This invention relates to insulated-gate fieldeffect transistor (IGFET) logic circuits and more particularly to a clocked IGFET logic circuit having provisions for reducing output noise caused by rapid charge sharing at its output terminal.
Clocked IGFET logic circuits which perform predetermined logical functions on a plurality of input signals synchronously with a system or subsystem clock are well known in the art. Generally, clocked IGFET logic circuits are dynamic and have the advantages of low power dissipation, high performance and low device count. A typical example of such a circuit includes a precharge transistor having its conduction channel connected between a V.sub.DD supply terminal and an output terminal, a functional network connected between the output terminal and a switch ground node, and a ground switch transistor having a conduction channel connected between the switch ground node and a V.sub.SS supply terminal. The functional network includes a plurality of transistors each having a gate connected to a respective one of a plurality of input signals and a conduction channel which is connected together with those of the other transistors of the functional network in a configuration which provides the circuit with the predetermined logical function. When the functional network includes transistors which have their conduction channels connected in series, the circuit may exhibit noise steps in the output signal caused by rapid charge sharing at the output terminal. This problem of noise steps is now explained with the aid of FIG. 1.
Referring now to FIG. 1 there is shown a schematic diagram of a clocked logic circuit 100 implemented in CMOS technology and operating between a positive V.sub.DD supply potential and a V.sub.SS supply potential which in the present case is ground. The supply potentials are applied to the circuit through a V.sub.DD supply terminal and a V.sub.SS supply terminal, respectively. A p-channel precharge transistor Q1 has its source electrode 101 connected to the V.sub.DD supply terminal and its drain electrode 102 connected to an OUTPUT terminal. Since IGFETs are in general bilateral devices the distinction between source and drain electrodes is not essential to the description of the circuit, and transistor Q1 can be described simply as having a conduction channel connected between the V.sub.DD and OUTPUT terminals. As is well known, the electrical conductance of the channel of an IGFET is controlled by the bias potential applied to the gate of the transistor and can be varied from a relatively high value when the transistor is driven into its ON state to a vanishingly small value when the transistor is driven into its OFF state.
Connected between the OUTPUT terminal and a switch ground node 104 is a functional network 105 containing four n-channel transistors Q2, Q3, Q4, and Q5 with their conduction channels connected in series and their gates respectively connected to four INPUT terminals 106 through 109. The series connection of the conduction channels of the transistors of the functional network provides the circuit with the NAND logical function performed on four input signals A0, A1, A2 and A3 received at the input terminals. The switch ground node 104 is coupled to the V.sub.SS supply terminal through the conduction channel of an n-channel ground switch transistor Q6.
Associated with each of the junctures of transistors Q2 through Q6 are parasitic distribution and junction capacitances denoted by C1, C2, C3, and C4. Capacitance C5 associated with the OUTPUT terminal includes the parasitic junction capacitances of transistors Q1 and Q2 as well as a load capacitance. The capacitance C5 is typically larger than any of the other parasitic capacitances.
The gate 103 of transistor Q1 and the gate 101 of transistor Q6 both receive a clock signal having CMOS logic levels of V.sub.DD for a logic "1" and V.sub.SS for a logic "0". When the clock signal is at a logic "0" level, the circuit is in a precharge phase with transistor Q1 turned ON and transistor Q6 turned OFF, and the OUTPUT terminal is pulled up to V.sub.DD through transistor Q1. When the clock signal is at a logic "1" level, the circuit is in an active phase with transistor Q1 turned OFF and transistor Q6 turned ON. Under these conditions, the logic level at the OUTPUT terminal is a NAND function of the state of the input signals A0 through A3. For example, if input signals A0 through A3 were all at the logic "1" level during the active phase, transistors Q2 through Q5 would all be turned ON creating a current path between the OUTPUT terminal and the switch ground node and causing the OUTPUT terminal to be pulled to the logic "0" level of V.sub.SS through the current path and transistor Q6. For all other states of the input signals A0 through A3 there would be no current path through the functional network and the OUTPUT terminal would be maintained at the logic "1" level (V.sub.DD) by the charge stored in the capacitance C5 at that terminal.
If in a given active phase A0 through A3 were all at the logic "1" level, parasitic capacitances C1 through C4 would all be discharged to ground potential (V.sub.SS). If in the following precharge phase A0 goes to the logic "0" level while A1 through A3 remain at the logic "1" level, C1 through C4 would remain discharged while C5 charges up to V.sub.DD. If in the next active phase A0 goes to the logic "1" level, A1 and A2 remain at the logic "1" level and A3 goes to the logic "0" level the potential level at the OUTPUT terminal is expected to remain at V.sub.DD (logic "1" level) owing to the NAND logic function. However, because capacitances C2, C3 and C4 were initially discharged, transistors Q2, Q3 and Q4 whose source electrodes are initially at V.sub.SS would temporarily turn ON when their gates are biased at V.sub.DD causing charge to flow rapidly from C5 into C2, C3, and C4 until those transistors are eventually turned OFF by the substrate bias effect. This rapid charge sharing between C2, C3, C4 and C5 causes the potential level at the OUTPUT terminal to exhibit a rapid drop or negative-going step. Such negative-going steps in the output signal of the circuit are undesirable inasmuch as the magnitudes of such steps may exceed the noise margin of another circuit which receives the output signal and trigger an erroneous switching of the receiving circuit.
Therefore, a need clearly exists for an improved clocked IGFET logic circuit which avoids the problem of noise steps caused by rapid charge sharing.